Characterisation of Physically Unclonable Functions at Design Stage

The evaluation of Physically Unclonable Function (PUFs) quality is an open problem, as the PUF represents a circuit signature which depends on process variation but also environmental conditions. Some metrics consisting in analysing the statistics of PUF outputs have been introduced. The considered metrics are often the randomness (max entropy), the uniqueness (two PUFs should be different), and the steadiness (Reliability of the result). The drawback of this statistical analysis is that the silicon is necessary, thus involving a long and costly chip manufacturing process without the certainty to obtain a highquality PUF. The objective of our research topic is to propose a new method which allows to evaluate a silicon PUF, based on delay elements, at design stage without the need to have the circuit. The essence of the method is based on a MonteCarlo simulation of the netlist in order to take into account the process variation and the environment. To be validated, this method requires a comparison between the simulation results and measurements on silicon. The first step of the study, which is presented in this paper, is to redefine the metrics in order to run Monte-Carlo simulation on delay elements. Thus the randomness, uniqueness and steadiness metrics are revised and expressed in term of probabilities. Experiments have been carried out to extract the metrics from measurements on CYCLONE II FPGAs with different PUF structures. Hence these metrics are used two compare the Arbiter PUF (APUF) and Loop PUF (LPUF) in order to validate their soundness.